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DS2172 bit error rate tester (bert) DS2172 022798 1/20 features ? generates/detects digital bit patterns for analyzing, evaluating and troubleshooting digital communica- tions systems ? operates at speeds from dc to 52 mhz ? programmable polynomial length and feedback taps for generation of any other pseudorandom pattern up to 32 bits in length including: 2 6 1, 2 9 1, 2 11 1, 2 15 1, 2 20 1, 2 23 1, and 2 32 1 ? programmable userdefined pattern and length for generation of any repetitive pattern up to 32 bits in length ? large 32bit error count and bit count registers ? software programmable bit error insertion ? fully independent transmit and receive sections ? 8bit parallel control port ? detects test patterns with bit error rates up to 10 2 pin assignment wr (r/w ) int vss lc rl rlos vdd ale (as) tl ad0 ad1 test vss ad2 ad3 ad4 ad5 ad6 ad7 vss vdd bts rd (ds) cs tdata tdis tclk vss vdd rclk rdis rdata DS2172 32pin tqfp 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 9 1011 12131415 16 32 31 30 29 28 27 26 25 description the DS2172 bit error rate tester (bert) is a software programmable test pattern generator, receiver, and analyzer capable of meeting the most stringent error performance requirements of digital transmission facili- ties. two categories of test pattern generation (pseudo- random and repetitive) conform to ccitt/itu o.151, o.152, o.153, and o.161 standards. the DS2172 operates at clock rates ranging from dc to 52 mhz. this wide range of operating frequency allows the DS2172 to be used in existing and future test equipment, transmis- sion facilities, switching equipment, multiplexers, dacs, routers, bridges, csus, dsus, and cpe equip- ment. the DS2172 user programmable pattern registers pro- vide the unique ability to generate loopback patterns required for t1, fractionalt1, smart jack, and other test procedures. hence the DS2172 can initiate the loopback, run the test, check for errors, and finally deac- tivate the loopback. the DS2172 consists of four functional blocks: the pat- tern generator, pattern detector, error counter, and con- trol interface. the DS2172 can be programmed to gen- erate any pseudorandom pattern with length up to 2 321 bits (see table 5, note 9) or any user programmable bit pattern from 1 to 32 bits in length. logic inputs can be used to configure the DS2172 for applications requiring gap clocking such as fractionalt1, switched56, dds, normal framing requirements, and perchannel test procedures. in addition, the DS2172 can insert single or 10 1 to 10 7 bit errors to verify equipment operation and connectivity.
DS2172 022798 2/20 1.0 general operation 1.1 pattern generation the DS2172 is programmed to generate a particular test pattern by programming the following registers: pattern set registers (psr) pattern length register (plr) polynomial tap register (ptr) pattern control register (pcr) error insertion register (eir) please see tables 4 and 5 for examples of how to pro- gram these registers in order to generate some stan- dard test patterns. once these registers are pro- grammed, the user will then toggle the tl (transmit load) bit or pin to load the pattern into the onboard pat- tern generation circuitry and the pattern will begin appearing at the tdata pin. 1.2 pattern synchronization the DS2172 expects to receive the same pattern that it transmitted. the synchronizer examines the data at rdata and looks for characteristics of the transmitted pattern. the user can control the onboard synchronizer with the sync enable and resync bits in the pattern control register. in pseudorandom mode, the received pattern is tested to see if it fits the polynomial generator as defined in the transmit side. for pseudorandom patterns, only the original pattern and an all ones pattern or an all zeros pattern will satisfy this test. synchronization in pseudo- random pattern mode should be qualified by using the ra1 and ra0 indicators in the status register. syn- chronization is declared after 34 + n bits are received without error, where n is the exponent in the polynomial from table 4. once in synchronization (sr0. = 1) any deviation from this pattern will be counted by the bit error count register. in repetitive pattern mode a received pattern of the same length as being transmitted will satisfy this test. synchronization in repetitive pattern mode should be qualified by using the ra1 and ra0 indicators in the status register and examining the pattern receive register (prr03). see section 10 for an explanation of the pattern receive register. once in synchroniza- tion (sr.0 = 1) any deviation from this pattern will be counted by the bit error count register. 1.3 ber calculation users can calculate the actual bit error rate (ber) of the digital communications channel by reading the bit error count out of the bit error count register (becr) and reading the bit count out of the bit count register (bcr) and then dividing the becr value with the bcr value. the user has total control over the integration period of the measurement. the lc (load count) bit or pin is used to set the integration period. 1.4 generating errors via the error insertion register (eir), the user can intentionally inject a particular error rate into the trans- mitted data stream. injecting errors allows users to stress communication links and to check the functional- ity of error monitoring equipment along the path. 1.5 powerup sequence on powerup, the registers in the DS2172 will be in a random state. the user must program all the internal registers to a known state before proper operation can be insured.
DS2172 022798 3/20 DS2172 functional block diagram figure 1 bts rd wr test ale cs int ad0ad7 parallel control port pattern generator error insertion transmit rate control receive pattern registers pattern detector bit counter bit error counter loopback mux receive rate control lc sync rl tl rdis rclk rdata tdis tclk tdata DS2172 pattern generation block diagram figure 2 xor dff dff dff dff xor eir.5 pcr.5 tap b feedback 0 1 n2 n1 tap a feedback notes: 1. tap a always equals length (n1) of pseudorandom or repetitive pattern. 2. tab b can be programmed to any feedback tap for pseudorandom pattern generation.
DS2172 022798 4/20 detailed pin description table 1 pin symbol type description 1 tl i transmit load. a positivegoing edge loads the pattern generator with the con- tents of the pattern set registers. the msb of the repetitive or pseudorandom pattern appears at tdata after the third positive edge of tclk from asserting tl. tl is logically or'ed with pcr.7 and should be tied to v ss if not used. see figure 8 for timing information. 2 ad0 i/o data bus. a 8bit multiplexed address/data bus. 3 ad1 i/o data bus. a 8bit multiplexed address/data bus. 4 test i test. set high to 3state all output pins (int , adx, tdata, rlos). should be tied to v ss to enable all outputs. 5 v ss signal ground. 0.0 volts. should be tied to local ground plane. 6 ad2 i/o data bus. a 8bit multiplexed address/data bus. 7 ad3 i/o data bus. a 8bit multiplexed address/data bus. 8 ad4 i/o data bus. a 8bit multiplexed address/data bus. 9 ad5 i/o data bus. a 8bit multiplexed address/data bus. 10 ad6 i/o data bus. a 8bit multiplexed address/data bus. 11 ad7 i/o data bus. a 8bit multiplexed address/data bus. 12 v ss signal ground. 0.0 volts. should be tied to local ground plane. 13 v dd positive supply. 5.0 volts. 14 bts i bus type select. strap high to select motorola bus timing; strap low to select intel bus timing. this pin controls the function of the rd (ds), ale(as), and wr (r/w ) pins. if bts = 1, then these pins assume the function listed in parenthe- sis (). 15 rd (ds) i read input (data strobe). 16 cs i chip select. must be low to read or write the port. 17 ale (as) i address latch enable (address strobe). a positive going edge serves to demultiplex the bus. 18 wr (r/w ) i write input (read/write). 19 int o alarm interrupt. flags host controller during conditions defined in status regis- ter. active low, open drain output. 20 v dd positive supply. 5.0 volts. 21 v ss signal ground. 0.0 volts. should be tied to local ground plane. 22 lc i load count. a positivegoing edge latches the current bit and bit error count into the user accessible bcr and becr registers and clears the internal count regis- ters. lc is logically or'ed with control bit pcr.4. should be tied to v ss if not used. 23 rlos o receive loss of sync. indicates the real time status of the receive synchro- nizer. active high output.
DS2172 022798 5/20 pin description type symbol 24 rl i receive load. a positivegoing edge loads the previous 32 bits of data received at rdata into the pattern receive registers. rl is logically or'ed with control bit pcr.3. should be tied to v ss if not used. 25 rdata i receive data. received nrz serial data, sampled on the rising edge of rclk. 26 rdis i receive disable. set high to prevent the data at rdata from being sampled. set low to allow bits at rdata to be sampled. should be tied to v ss if not used. see figure 6 for timing information. all receive side operations are disabled when rdis is high. 27 rclk i receive clock. input clock from transmission link. 0 to 52 mhz. can be a gapped clock. fully independent from tclk. 28 v dd positive supply. 5.0 volts. 29 v ss signal ground. 0.0 volts. should be tied to local ground plane. 30 tclk i transmit clock. transmit demand clock. 0 to 52 mhz. can be a gapped clock. fully independent of rclk. 31 tdis i transmit disable. set high to hold the current bit being transmitted at tdata. set low to allow the next bit to appear at tdata. should be tied to v ss if not used. see figure 7 for timing information. all transmit side operations are disabled when tdis is high. 32 tdata o transmit data. transmit nrz serial data, updated on the rising edge of tclk.
DS2172 022798 6/20 DS2172 register map table 2 address r/w register name 00 r/w pattern set register 3. 01 r/w pattern set register 2. 02 r/w pattern set register 1. 03 r/w pattern set register 0. 04 r/w pattern length register. 05 r/w polynomial tap register. 06 r/w pattern control register. 07 r/w error insert register. 08 r bit counter register 3. 09 r bit counter register 2. 0a r bit counter register 1. 0b r bit counter register 0. 0c r bit error counter register 3. 0d r bit error counter register 2. 0e r bit error counter register 1. 0f r bit error counter register 0. 10 r pattern receive register 3. 11 r pattern receive register 2. 12 r pattern receive register 1. 13 r pattern receive register 0. 14 r status register. 15 r/w interrupt mask register. 1c r/w test register (see note 1) note: 1. the test register must be set to 00 hex to insure proper operation of the DS2172. 2.0 parallel control interface the DS2172 is controlled via a multiplexed bidirec- tional address/data bus by an external microcontroller or microprocessor. the DS2172 can operate with either intel or motorola bus timing configurations. if the bts pin is tied low, intel timing will be selected; if tied high, motorola timing will be selected. all motorola bus sig- nals are listed in parenthesis (). see the timing dia- grams in the a.c. electrical characteristics for more details. the multiplexed bus on the DS2172 saves pins because the address information and data information share the same signal paths. the addresses are pres- ented to the pins in the first portion of the bus cycle and data will be transferred on the pins during second por- tion of the bus cycle. addresses must be valid prior to the falling edge of ale(as), at which time the DS2172 latches the address from the ad0 to ad7 pins. valid write data must be present and held stable during the later portion of the ds or wr pulses. in a read cycle, the DS2172 outputs a byte of data during the latter portion of the ds or rd pulses. the read cycle is terminated and the bus returns to a high impedance state as rd transi- tions high in intel timing or as ds transitions low in moto- rola timing. the DS2172 can also be easily connected to nonmultiplexed buses. rclk and tclk are used to update counters and load transmit and receive pattern registers. at slow clock rates, sufficient time must be allowed for these port operations. 3.0 pattern set registers the pattern set registers (psr) are loaded each time a new pattern (whether it be pseudorandom or repetitive) is to be generated. when a pseudorandom pattern is generated, all four psrs must be loaded with ff hex. when a repetitive pattern is to be created, the four psrs are loaded with the pattern that is to be repeated. please see tables 4 and 5 for some programming examples.
DS2172 022798 7/20 pattern set registers (msb) (lsb) ps31 ps30 ps29 ps28 ps27 ps26 ps25 ps24 ps23 ps22 ps21 ps20 ps19 ps18 ps17 ps16 ps15 ps14 ps13 ps12 ps11 ps10 ps9 ps8 ps7 ps6 ps5 ps4 ps3 ps2 ps1 ps0 4.0 pattern length register length bits lb4 to lb0 determine the length of the pseudorandom polynomial or programmable repetitive pattern that is generated and detected. with the pseudorandom patterns, the atap ao feedback position of the pattern generator is always equal to the value in the pattern length register (plr). please refer to fig- ure 2 for a block diagram of the pattern generator and to tables 4 and 5 for some programming examples. plr: pattern length register (address=04 hex) (msb) (lsb) lb4 lb3 lb2 lb1 lb0 symbol position name and description plr1.7 not assigned. should be set to 0 when written to. plr1.6 not assigned. should be set to 0 when written to. plr1.5 not assigned. should be set to 0 when written to. lb4 plr1.4 length bit 4. lb3 plr1.3 length bit 3. lb2 plr1.2 length bit 2. lb1 plr1.1 length bit 1. lb0 plr1.0 length bit 0. 5.0 polynomial tap register polynomial tap bits pt4 pt0 determine the feedback position of tap b connected to the xor input of the pat- tern generator. feedback tap b provides one of two feedback paths within the pattern generator. please refer to figure 2 for a block diagram of the pattern gener- ator and to tables 4 and 5 for register programming examples. ptr: polynomial tap register (address=05 hex) (msb) (lsb) pt4 pt3 pt2 pt1 pt0 symbol position name and description ptr.7 not assigned. should be set to 0 when written to. ptr.6 not assigned. should be set to 0 when written to. ptr.5 not assigned. should be set to 0 when written to. pt4 ptr.4 polynomial tap bit 4. psr3 (addr.=00 hex) psr2 (addr.=01 hex) psr1 (addr.=02 hex) psr0 (addr.=03 hex)
DS2172 022798 8/20 pt3 ptr.3 polynomial tap bit 3. pt2 ptr.2 polynomial tap bit 2. pt1 ptr.1 polynomial tap bit 1. pt0 ptr.0 polynomial tap bit 0. 6.0 pattern control register the pattern control register (pcr) is used to configure the operating parameters of the DS2172 and to control the patterns being generated and received. also the pcr is used to control the pattern synchronizer and the error and bit counters. pcr: pattern control register (address=06 hex) (msb) (lsb) tl qrss ps lc rl synce resync lpbk symbol position name and description tl pcr.7 transmit load. a low to high transition loads the pattern generator with the contents of the pattern set registers. pcr.7 is logically ored with the input pin tl. must be cleared and set again for subsequent loads. qrss pcr.6 zero suppression select. forces a aoneo into the pattern whenever the next 14 bit positions are all azeroso. should only be set when using the qrss pattern. 0 = zero suppression disabled 1 = zero suppression enabled ps pcr.5 pattern select. 0 = repetitive pattern 1 = pseudorandom pattern lc pcr.4 latch count registers. a low to high transition latches the bit and error counts into the user accessible registers bcr and becr and clears the internal register count. pcr.4 is logically or'ed with input pin lc. must be cleared and set again for subsequent loads. rl pcr.3 receive data load. a transition from low to high loads the previous 32 bits of data received at rdata into the pattern receive registers (prr). pcr.3 is logically or'ed with input pin rl. must be cleared and set again for subsequent latches. synce pcr.2 sync enable. 0 = auto resync is enabled. 1 = auto resync is disabled. resync pcr.1 initiate manual resync process. a low to high transition will force the DS2172 to resynchronize to the incoming pattern at rdata. must be cleared and set again for a subsequent resync. lpbk pcr.0 transmit/receive loopback select. when enabled, the rdata input is disabled; tdata continues to output data as normal. see figure 1. 0 = loopback disabled 1 = loopback enabled
DS2172 022798 9/20 7.0 error insert register the error insertion register (eir) controls circuitry within the DS2172 that allows the generated pattern to be intentionally corrupted. bit errors can be inserted automatically at regular intervals by properly program- ming the eir0 to eir2 bits or bit errors can be inserted at random (under microcontroller control) via the eir.3 bit. eir: error insert register (address=07 hex) (msb) (lsb) tinv rinv sbe eir2 eir1 eir0 symbol position name and description eir.7 not assigned. should be set to 0 when written to. eir.6 not assigned. should be set to 0 when written to. tinv eir.5 transmit data inversion select. 0 = do not invert data to be transmitted at tdata 1 = invert data to be transmitted at tdata rinv eir.4 receive data inversion select. 0 = do not invert data received at rdata 1 = invert data received at rdata sbe eir.3 single bit error insert. a low to high transition will create a single bit error. must be cleared and set again for a subsequent bit error to be inserted. can be used to accomplish rates not addressed in table 3 (e.g., ber of less than 10 7 ). eib2 eir.2 error insert bit 2. see table 3. eib1 eir.1 error insert bit 1. see table 3. eib0 eir.0 error insert bit 0. see table 3. error bit insertion table 3 eib2 eib1 eib0 error rate inserted 0 0 0 no errors automatically inserted 0 0 1 10 1 0 1 0 10 2 0 1 1 10 3 1 0 0 10 4 1 0 1 10 5 1 1 0 10 6 1 1 1 10 7
DS2172 022798 10/20 pseudorandom pattern generation (pcr.5=1) table 4 pattern type ptr plr psr3 psr2 psr1 psr0 tinv rinv 2 3 1 00 02 ff ff ff ff 0 0 2 4 1 00 03 ff ff ff ff 0 0 2 5 1 01 04 ff ff ff ff 0 0 2 6 1 04 05 ff ff ff ff 0 0 2 7 1 00 06 ff ff ff ff 0 0 2 7 1 fractional t1 lb activate 03 06 ff ff ff ff 0 0 2 7 1 fractional t1 lb deactivate 03 06 ff ff ff ff 1 1 2 9 1 o.153 (511 type) 04 08 ff ff ff ff 0 0 2 10 1 02 09 ff ff ff ff 0 0 2 11 1 o.152 and o.153 (2047 type) 08 0a ff ff ff ff 0 0 2 15 1 o.151 0d 0e ff ff ff ff 1 1 2 17 1 02 10 ff ff ff ff 0 0 2 18 1 06 11 ff ff ff ff 0 0 2 20 1 o.153 02 13 ff ff ff ff 0 0 2 20 1 o.151 qrss (pcr.6=1) 10 13 ff ff ff ff 0 0 2 21 1 01 14 ff ff ff ff 0 0 2 22 1 00 15 ff ff ff ff 0 0 2 23 1 o.151 11 16 ff ff ff ff 1 1 2 25 1 02 18 ff ff ff ff 0 0 2 28 1 02 1b ff ff ff ff 0 0 2 29 1 01 1c ff ff ff ff 0 0 2 31 1 02 1e ff ff ff ff 0 0 2 32 1 (see note below) 10 1f ff ff ff ff 0 0
DS2172 022798 11/20 repetitive pattern generation (pcr.5=0) table 5 pattern type ptr plr psr3 psr2 psr1 psr0 tinv rinv all ones 00 00 ff ff ff ff 0 0 all zeros 00 00 ff ff ff fe 0 0 alternating ones and zeros 00 01 ff ff ff fe 0 0 double alternating ones and zeros 00 03 ff ff ff fc 0 0 3 in 24 00 17 ff 20 00 22 0 0 1 in 16 00 0f ff ff 00 01 0 0 1 in 8 00 07 ff ff ff 01 0 0 1 in 4 00 03 ff ff ff f1 0 0 d4 line loopback activate 00 04 ff ff ff f0 0 0 d4 line loopback deactivate 00 02 ff ff ff fc 0 0 notes for tables 4 and 5: 1. ptr = polynomial tap register (address = 05) 2. plr = pattern length register (address = 04) 3. psr3 = pattern set register 3 (address = 00) 4. psr2 = pattern set register 2 (address = 01) 5. psr1 = pattern set register 1 (address = 02) 6. psr0 = pattern set register 0 (address = 03) 7. tinv = transmit data inversion select bit (eir.5) 8. rinv = receive data inversion select bit (eir.4) 9. for the 2 32 1 pattern, the random pattern actually repeats every (4093 x 2 20 ) + 1046529 bits instead of 2 32 1. 8.0 bit count registers the bit count registers (bcr3 to bcr0) comprise a 32bit count of bits (actually rclk cycles) received at rdata. bc31 is the msb of the 32 bit count. the bit counter increments for each cycle of rclk when input pin rdis is low. the bit counter is disabled during loss of sync. the status register bit bcof is set when this 32bit register overflows. upon an overflow condition, the user must clear the bcr by either toggling the lc bit or pin. the DS2172 latches the bit count into the bcr registers and clears the internal bit count when either the pcr.4 bit or the lc input pin toggles from low to high. the bit count and bit error count (available via the becrs) are used by an external processor to compute the ber performance on a loop or channel basis. bit count registers (msb) (lsb) bc31 bc30 bc29 bc28 bc27 bc26 bc25 bc24 bc23 bc22 bc21 bc20 bc19 bc18 bc17 bc16 bc15 bc14 bc13 bc12 bc11 bc10 bc9 bc8 bc7 bc6 bc5 bc4 bc3 bc2 bc1 bc0 bcr3 bcr2 bcr1 bcr0 (addr.=08 hex) (addr.=09 hex) (addr.=0a hex) (addr.=0b hex)
DS2172 022798 12/20 9.0 bit error count registers the bit error count registers (becr3 to becr0) com- prise a 32bit count of bits received in error at rdata. the bit error counter is disabled during loss of sync. bec31 is the msb of the 32 bit count. the status regis- ter bit becof is set when this 32bit register overflows. upon an overflow condition, the user must clear the becr by either toggling the lc bit or pin. the DS2172 latches the bit error count into the becr registers and clears the internal bit error count when either the pcr.4 bit or the lc input pin toggles from low to high. the bit count (available via the bcrs) and bit error count are used by an external processor to compute the ber per- formance on a loop or channel basis. bit error count registers (msb) (lsb) bec31 bec30 bec29 bec28 bec27 bec26 bec25 bec24 bec23 bec22 bec21 bec20 bec19 bec18 bec17 bec16 bec15 bec14 bec13 bec12 bec11 bec10 bec9 bec8 bec7 bec6 bec5 bec4 bec3 bec2 bec1 bec0 10.0 pattern receive registers the pattern receive register (prr) provide access to the data patterns received at rdata. the operation of these registers depends on the synchronization status of the DS2172. asserting the rl bit (pcr.3) or pin dur- ing an outof sync condition (sr.0 = 0) will latch the previous 32 bits of data received at rdata into the prr registers. when the DS2172 is in sync (sr.0 = 1) asserting rl will latch the pattern that to which the device has established synchronization. since the receiver has no knowledge of the start or end of the pat- tern, the data in the prr registers will have no particular alignment. as an example, if the receiver has synchro- nized to the pattern 00100110, prr1 may report 10011000, 11000100 or any rotation thereof. once syn- chronization is established, bit errors cannot be viewed in the prr registers. pattern receive registers (msb) (lsb) pr31 pr30 pr29 pr28 pr27 pr26 pr25 pr24 pr23 pr22 pr21 pr20 pr19 pr18 pr17 pr16 pr15 pr14 pr13 pr12 pr11 pr10 pr9 pr8 pr7 pr6 pr5 pr4 pr3 pr2 pr1 pr0 11.0 status register and interrupt mask register the status register (sr) contains information on the current real time status of the DS2172. when a particu- lar event has occurred, the appropriate bit in the register will be set to a one. all of the bits in these registers (except for the sync bit) operate in a latched fashion. this means that if an event occurs and a bit is set to a one in any of the registers, it will remain set until the user reads that bit. for the bed, bcof, and becof status bits, they will be cleared when read and will not be set again until the event has occurred again. for rlos, ra0, and ra1 status bits, they will be cleared when read if the condition no longer persists. the sr register has the unique ability to initiate a hard- ware interrupt via the int pin. each of the alarms and events in the sr can be either masked or unmasked from the interrupt pins via the interrupt mask register (imr). sr: status register (address=14 hex) (msb) (lsb) ra1 ra0 rlos bed bcof becof sync becr3 becr2 becr1 becr0 (addr.=0c hex) (addr.=0d hex) (addr.=0e hex) (addr.=0f hex) prr3 prr2 prr1 prr0 (addr.=10 hex) (addr.=11 hex) (addr.=12 hex) (addr.=13 hex)
DS2172 022798 13/20 symbol position name and description sr.7 not assigned. could be any value when read. ra1 sr.6 receive all ones. set when 32 consecutive ones are received; allowed to be cleared when a zero is received. ra0 sr.5 receive all zeros. set when 32 consecutive zeros are received; allowed to be cleared when a one is received. rlos sr.4 receive loss of sync. set when the device is searching for synchroniza- tion. once sync is achieved, will remain set until read. bed sr.3 bit error detection. set when bit errors are detected. bcof sr.2 bit counter overflow. set when the 32bit bcr overflows. becof sr.1 bit error count overflow. set when the 32bit becr overflows. sync sr.0 sync. real time status of the synchronizer (this bit is not latched). will be set when synchronization is declared. will be cleared when 6 or more bits out of 64 are received in error (if pcr.2 = 0). imr: interrupt mask register (address=15 hex) (msb) (lsb) ra1 ra0 rlos bed bcof becof sync symbol position name and description imr.7 not assigned. should be set to zero when written to. ra1 imr.6 receive all ones. 0 = interrupt masked 1 = interrupt enabled ra0 imr.5 receive all zeros. 0 = interrupt masked 1 = interrupt enabled rlos imr.4 receive loss of sync. 0 = interrupt masked 1 = interrupt enabled bed imr.3 bit error detection. 0 = interrupt masked 1 = interrupt enabled bcof imr.2 bit counter overflow. 0 = interrupt masked 1 = interrupt enabled becof imr.1 bit error count overflow. 0 = interrupt masked 1 = interrupt enabled sync imr.0 sync. 0 = interrupt masked 1 = interrupt enabled
DS2172 022798 14/20 12.0 ac timing and dc operating characteristics absolute maximum ratings* voltage on any pin relative to ground 1.0v to +7.0v operating temperature 0 c to 70 c storage temperature 55 c to +125 c soldering temperature 260 c for 10 seconds * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. recommended dc operating conditions (0 c to 70 c) parameter symbol min typ max units notes logic 1 v ih 2.0 v dd +0.3 v logic 0 v il 0.3 +0.8 v supply v dd 4.50 5.50 v capacitance (t a =25 c) parameter symbol min typ max units notes input capacitance c in 5 pf output capacitance c out 7 pf dc characteristics (0 c to 70 c; v dd =5v 10%) parameter symbol min typ max units notes supply current @ 5v i dd 10 ma 1 input leakage i il 1.0 +1.0 m a 2 output leakage i lo 1.0 m a 3 output current @ 2.4v i oh 1.0 ma output current @ 0.4v i ol +4.0 ma notes: 1. tclk = rclk = 1.544 mhz; outputs open circuited. 2. 0.0v < v in < v dd 3. applies to int when tristated.
DS2172 022798 15/20 ac characteristics parallel port (0 c to 70 c; v dd =5v 10%) parameter symbol min typ max units notes cycle time t cyc 200 ns pulse width, ds low or rd high pw el 100 ns pulse width, ds high or rd low pw eh 100 ns input rise/fall times t r , t f 20 ns r/w hold time t rwh 10 ns r/w setup time before ds high t rws 50 ns cs setup time before ds, wr or rd active t cs 20 ns cs hold time t ch 0 ns read data hold time t dhr 5 50 ns write data hold time t dhw 0 ns mux'ed address valid to as or ale fall t asl 15 ns mux'ed address hold time t ahl 10 ns delay time ds, wr or rd to as or ale rise t asd 20 ns pulse width as or ale high pw ash 30 ns delay time, as or ale to ds, wr or rd t ased 10 ns output data delay time from ds or rd t ddr 5 50 ns data setup time t dsw 50 ns
DS2172 022798 16/20 intel bus read ac timing (bts=0) figure 3 t cyc t ased pw eh pw el t cs pw ash t ddr t ahl t dhr t ch t asl t asd t asd ale wr rd cs ad0ad7 intel bus write ac timing (bts=0) figure 4 t cyc pw ash pw eh pw el t dsw t cs t asd t asd t ased t asl t dhw t ch t ahl ale rd wr cs ad0ad7
DS2172 022798 17/20 motorola bus ac timing (bts=1) figure 5 t ased pw eh pw el t cyc t dsw pw ash t asd t rws t rwh t dhr t ddr t ahl t asl t ahl t dhw t ch t asl t cs as ds r/w ad0ad7 (read) cs ad0ad7 (write)
DS2172 022798 18/20 ac characteristics receive side (0 c to 70 c; v dd =5v 10%) parameter symbol min typ max units notes rclk period t cp 19 ns rclk pulse width t ch t cl 8 8 ns ns rdata set up to rclk rising t su1 4 ns rdata hold from rclk rising t hd1 0 ns rdis set up to rclk rising t su2 4 ns rdis hold from rclk rising t hd2 0 ns rl and lc pulse width t wrl 25 ns rlck rise and fall times t r , t f 10 ns 1 ac characteristics transmit side (0 c to 70 c; v dd =5v 10%) parameter symbol min typ max units notes tclk period t cp 19 ns tclk pulse width t ch t cl 8 8 ns ns tdata delay from tclk rising t dd 9 ns tdis set up to tclk rising t su 4 ns tdis hold from tclk rising t hd 0 ns tl pulse width t wtl 15 ns tl set up to tclk rising t stl 4 ns tl hold off from tclk rising t htl 0 ns tclk rise and fall time t r , t f 10 ns 1 note: 1. the maximum rise and fall time is either 10 ns or 10% of t cp whichever is less.
DS2172 022798 19/20 receive ac timing figure 6 t r t f t su1 t su2 t hd1 t hd2 t wrl t cp t ch t cl rclk rdata rdis rl/lc transmit ac timing figure 7 tclk tdata tdis see note below t cp t cl t ch t hd t su t dd t f t r note: when tdis is high about the rising edge of tclk, tdata will not be updated and will be held with the previous valve until tdis is low about the rising edge of tclk. transmit ac timing for the tl input figure 8 tclk tdata tl t stl t wtl t htl note: the rising edge of tl causes the internal pattern generation circuitry to be reloaded; the first bit of the new pattern (the shaded one) will appear after two tclk periods.
DS2172 022798 20/20 DS2172 32pin tqfp gauge

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